Cambridge A-Level Computer Science (9618) · lesson 11 of 15 · 30 min
Von Neumann Architecture
The Von Neumann architecture stores both program instructions and data in the same memory, accessed via the same bus. This creates the Von Neumann bottleneck: the CPU can only fetch one item (instruction or data) per clock cycle, limiting performance.
Harvard Architecture
The Harvard architecture uses separate memory and buses for instructions and data. The CPU can fetch an instruction and read/write data simultaneously — eliminating the bottleneck.
Used in: microcontrollers (Arduino, PIC), DSPs (digital signal processors), and modern CPU caches (L1 cache is split into instruction cache and data cache — a modified Harvard design).
Comparison
Contemporary Processors
Modern CPUs use a modified Harvard architecture internally: the L1 cache is split into separate instruction cache (I-cache) and data cache (D-cache), allowing simultaneous fetch and data access. The external interface to main RAM is Von Neumann.
What is the Von Neumann bottleneck?
- The CPU runs too hot
- Instructions and data share the same bus, limiting throughput
- RAM is too slow
- The ALU cannot handle floating-point
Answer: Instructions and data share the same bus, limiting throughput
The shared bus means the CPU can only fetch one item per cycle — either an instruction or data, not both.
Harvard architecture is commonly used in:
- Desktop PCs
- Microcontrollers and DSPs
- Mainframes
- Cloud servers
- Answer: 1
Harvard architecture is used in embedded systems and DSPs where performance and predictability matter.
Modern CPUs use a modified Harvard design. What does this mean?
- They have no cache
- The L1 cache is split into separate instruction and data caches
- They use two separate CPUs
- They have no Von Neumann features
Answer: The L1 cache is split into separate instruction and data caches
Modern CPUs split the L1 cache into I-cache and D-cache (Harvard internally) but present a unified Von Neumann interface to RAM.
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