Cambridge A-Level Computer Science (9618) · lesson 13 of 15 · 30 min
What Is Pipelining?
Pipelining overlaps the execution of multiple instructions by dividing the fetch-decode-execute cycle into stages. While one instruction is being executed, the next is being decoded, and the one after that is being fetched — like an assembly line.
A 3-stage pipeline (Fetch, Decode, Execute) can have 3 instructions in flight simultaneously, ideally tripling throughput.
Pipeline Hazards
Superscalar and Out-of-Order Execution
Superscalar processors have multiple execution units and can issue more than one instruction per clock cycle. Out-of-order execution allows the CPU to execute instructions in a different order than the program specifies, as long as dependencies are respected — filling pipeline stalls with independent instructions.
Parallel Processing
In a 5-stage pipeline, how many instructions can be in flight simultaneously?
- 1
- 3
- 5
- 10
Answer: 5
Each stage processes a different instruction simultaneously — 5 stages = 5 instructions in flight.
A control hazard occurs when:
- Two instructions need the same register
- A branch instruction makes the next instruction unknown
- Memory is too slow
- The ALU is busy
- Answer: 1
Branch instructions create control hazards because the CPU doesn’t know which instruction to fetch next until the branch is resolved. Out-of-order execution allows the CPU to:
- Run instructions on multiple cores
- Execute instructions in a different order to avoid stalls
- Predict branch outcomes
- Access memory faster
- Answer: 1
Out-of-order execution reorders independent instructions to keep the pipeline busy during stalls.
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