IB CS Core — Topics 1–5 (SL & HL) · lesson 1 of 4 · 30 min
CPU architecture: ALU, CU, registers, buses
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CPU architecture: ALU, CU, registers, and buses
The Central Processing Unit (CPU) is the brain of a computer. The IB CS syllabus requires you to understand the function of each component and how they interact during the fetch-decode-execute cycle.
The fetch-decode-execute cycle
Every instruction a CPU runs goes through three stages: Fetch: The PC contains the address of the next instruction. The CU copies this address to the MAR, then retrieves the instruction from memory into the MDR, then copies it to the IR. The PC is incremented to point to the next instruction. Decode: The CU interprets the instruction in the IR, identifying the operation code (opcode) and operand(s). Execute: The CU sends control signals to the appropriate components. If arithmetic is needed, the ALU performs it and stores the result in the ACC. If memory access is needed, the MAR and MDR are used. Worked trace: ADD 5
- PC = 100. MAR ← 100. Fetch instruction from address 100 → MDR. IR ← MDR. PC ← 101.
- CU decodes IR: opcode = ADD, operand = 5.
- ALU adds 5 to current ACC value. Result stored in ACC.
Buses
Components communicate via three buses: Bus width determines capacity: a 32-bit address bus can address 2³² = 4 GB of memory. A 64-bit address bus can address 2⁶⁴ bytes — far more than any current system uses. IB Paper 1 questions often ask you to state the function of a specific register or describe one stage of the fetch-decode-execute cycle. Use precise terminology: “The PC is incremented” not “the computer moves to the next instruction.”
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